▪ W1 and W2, as well as V1 and V2< must be externally connected to each other.▪ If not using the Current Limiter (OCL) function, leave the OCL and SD pins open, but the SD pin should be connected toGND if significant external noise is observed.▪ Place a pull-up resistor, RFO , between the 3.3 V or 5 V supply and the IC, selected according to anti-noise characteristics,even though a 1 MΩ pull-up resistor is built-in at the ¯ F¯O¯ pin. Note that connecting to the 3.3 V or 5 V supply without a pull-upresistor disables the TSD function (however, low-side UVLO protection and OCP function remain active).▪ To avoid malfunctions resulting from noise interference, place a 0.001 to 0.01 μF ceramic capacitor (CFO) between the ¯ F ¯O¯and COM2 pins.▪ To avoid malfunctions resulting from noise interference, the traces must be as short as possible between the IC and thebootstrap capacitors, Cbootx (approximately 1 μF).▪ To avoid malfunctions resulting from noise interference, place a 0.01 to 0.1 μF ceramic capacitor between the VCC1 andCOM1 pins, as well as between the VCC2 and COM2 pins. Also, the traces between them must be as short as possible.▪ To avoid malfunctions resulting from noise interference, the traces between the current sense resistor RS, which is placedbetween the LS and COM2 pins, and the IC must be as short and wide as possible.▪ To avoid malfunction, the wiring between the LS and COM2 pins should be as short as possible. When wiring cannot beshortened sufficiently, insert a fast diode between LS and COM2.
▪ W1 and W2, as well as V1 and V2< must be externally connected to each other.<br>▪ If not using the Current Limiter (OCL) function, leave the OCL and SD pins open, but the SD pin should be connected to<br>GND if significant external noise is observed.<br>▪ Place a pull-up resistor, RFO , between the 3.3 V or 5 V supply and the IC, selected according to anti-noise characteristics,<br>even though a 1 MΩ pull-up resistor is built-in at the ¯ F¯O¯ pin. Note that connecting to the 3.3 V or 5 V supply without a pull-up<br>resistor disables the TSD function (however, low-side UVLO protection and OCP function remain active).<br>▪ To avoid malfunctions resulting from noise interference, place a 0.001 to 0.01 μF ceramic capacitor (CFO) between the ¯ F ¯O¯<br>and COM2 pins.<br>▪ To avoid malfunctions resulting from noise interference, the traces must be as short as possible between the IC and the<br>bootstrap capacitors, Cbootx (approximately 1 μF).<br>▪ To avoid malfunctions resulting from noise interference, place a 0.01 to 0.1 μF ceramic capacitor between the VCC1 and<br>COM1 pins, as well as between the VCC2 and COM2 pins. Also, the traces between them must be as short as possible.<br>▪ To avoid malfunctions resulting from noise interference, the traces between the current sense resistor RS, which is placed<br>between the LS and COM2 pins, and the IC must be as short and wide as possible.<br>▪ To avoid malfunction, the wiring between the LS and COM2 pins should be as short as possible. When wiring cannot be<br>shortened sufficiently, insert a fast diode between LS and COM2.
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