The subsystem provides an AXI4-Lite

The subsystem provides an AXI4-Lite bus interface for a simple connection to the processor core to allow access to the registers. This AXI4-Lite slave interface supports single beat read and write data transfers (no burst transfers). 32-bit AXI4-Stream buses are provided for moving transmit and receive Ethernet data to and from the subsystem. These buses are designed to be used with an AXI Direct Memory Access (DMA) IP or AXI Multichannel Direct Memory Access (MCDMA) IP core, AXI4-Stream Data FIFO, or any other custom logic in any supported device. The AXI4-Stream buses are designed to provide support for TCP/UDP partial or full checksum offload in hardware if required. The AXI4-Stream buses are described in Frame Transmission.The PHY side of the subsystem is connected to an off-the-shelf Ethernet PHY device, which performs the BASE-T standard at 1 Gbps, 100 Mbps, and 10 Mbps speeds. The PHY device can be connected using any of the following supported interfaces: GMII/MII, RGMII, or, by using the1G/2.5G Ethernet PCS/PMA or SGMII module.