Use VHDL language to output the tri

Use VHDL language to output the triangle wave, square wave and each module designed by waveform control, frequency control and subprogram of each module to the image file. The circuit also calls the graphic module in the edit box to edit the circuit diagram. Key 1 uses Delta, Delta Control the rectangle and identification waveform. Finally, connect the 8-bit output with the data port of ad 0832, and convert it through D / A. you can see the output waveform grating in the oscilloscope. Click the button several times to output multiple frequency waveforms, 10 in NiosII Output bit frequency controller, switch to corresponding net output. Please input clock CLK with skew module. One by one experience VHD frequency calculation A. reduce a to 0, and the output will be tracked. Triangle wave module (delta), rectangle wave module (quadrangle), signal wave module (quadrangle) The input clock of the module (SIN) CLK. The variable defined by vhd0.000111-10000 is TMP. Each input pulse will be changed into + 8 or 8 TMP respectively and sent to output Q to generate triangle wave signal. Set the square VHD variable CNT of rectangular wave module, and make sure that all input pulses are less than 32. Less than 32 below 32. Output the higher level to CNT + L, otherwise the output will be lower, CNT will be assigned to 0, generate a rectangular signal, which is used to identify the pie module VHD. Define the signature pie data table. The signature data of each pulse search will be corresponding Four Yin wave shape is generated by continuous printing. VHD. Control the selection of output waveform.