According to the j-v curve, EQE and

According to the j-v curve, EQE and performance parameters, as shown in figure 4.5 and table 4.2, when the back surface of crystalline silicon is directly in contact with Al, the VOC and FF of the device are lower, resulting in lower PCE of the battery. This is due to the direct contact between the crystalline silicon and Al, the formation of ohmic contact without high temperature annealing, and the existence of schottky barrier. Moreover, because the interface between crystal silicon and Al is not effectively passivated, many defects lead to serious carrier complex in the battery, so the performance of the device is reduced. When the intrinsic amorphous silicon film (i-a-si :H) is used to passivate the surface of the silicon wafer and n-a-si :H is used as the back field, the performance of the device is obviously improved. JSC, VOC, FF and PCE of the battery all increased significantly, JSC increased from 26.4 mA/cm2 to 29.7 mA/cm2, and the short-circuit current density obtained by the test integral of external quantum efficiency (EQE) was consistent with the test result of j-v. VOC and FF increased from 548 mV and 56.1% to 620 mV and 65.8% respectively, and the PCE of the device increased from 8.3% to 12.1%. This is due to the passivation of intrinsic amorphous silicon film (i-a-si :H) on the surface of the silicon wafer, which improves the sub-lifetime and diffusion length of the silicon wafer and reduces the carrier recombination. Moreover, as n-a-si :H forms ohmic contact with Al, the interface resistance is reduced. The Rsh of the device is one of the indexes of the performance of the device. The larger the Rsh, the larger the VOC and FF of the device; on the contrary, the smaller the Rsh, the smaller the VOC and FF of the device. Based on (I, n) a - Si: H of the preparation of a formal PEDOT: PSS/c - Si solar cell Rsh is bigger, Rsh from 0.34 k Ω cm2 increases to 1.91 k Ω cm2, big Rsh reduce shunt paths of device, improve the battery performance.