Low-Power Design of CMOS ICArguably

Low-Power Design of CMOS ICArguably, invention of the transistor was a giant leap forward for low-power microelectronics that has remained unequal to date, even by the virtual torrent of developments it forbore. Operation of vacuum tube required several hundred volts of anode voltage and a few watts of power. In comparison, the transistor required only milliwatts of power. Since the invention of the transistor, decades ago, through the years leading to the 1990s, power dissipation, though not entirely ignored, was of little. The greater emphasis was on performance and miniaturization. Applications are applied to a battery-pocket calculator, hearing aids, implantable pacemakers, portable military equipment used by individual soldier and most important wrist-watches-drove low-power electronics. In all such applications, it is important to prolong the battery life as much as possible. And now, with the growing trend towards portable computing and wireless communication, power dissipation has become one of the most critical factors in the continued development of the microelectronics technology. There are three sources of power dissipation in a digital complementary metal-oxide-semiconductor (CMOS) circuit. The first source is the logic transitions. As the" nodes " in a digital CMOS circuit transition back and forth between the two logic levels, the parasitic capacitances are charged and discharged. Current flows through the channel resistance of the transistors, and electrical energy is converted into heat and dissipated away. As suggested by this informal description, this component of power dissipation is proportional to the supply voltage, node voltage swing, and the average switched capacitance per cycle. The second source of power dissipation is the short-circuit currents that flow directly from supply to ground when the n-subnetwork and the p-subnetwork of a CMOS gate both conduct simultaneously. The third and the last source of dissipation is the leakage current that flows when the input (s) to, and therefore the outputs of a gate is not changing. This is called static dissipation. In current day technology the magnitude of leakage current is low and usually neglected. As the supply voltage is being scaled down to reduce dynamic power, however, MOS field-effect transistors (MOSFETs) with low threshold voltages have to be used. The lower the threshold voltage. the lower the degree to which MOSFETs in the logic gates are turned off and the higher is the standby leakage current. The power dissipation attributable to the three sources described above can be influenced at different levels of the overall design process. Since the dominant component of power dissipation in CMOS circuits varies as the square of the supply voltage, significant savings in power dissipation can be obtained from operation at a reduced supply voltage. If the supply voltage is reduced while the threshold voltages stay the same, that will reduce the noise margins are reduced. To improve noise margins, the threshold voltages need to be made smaller as well. However, the subthreshold leakage current increases exponentially when the threshold voltage is reduced. The higher static dissipation may offset the reduction in transitions component of the dissipation. Hence the devices need to be designed to have threshold voltages that maximize the net reduction in the dissipation. The transitions component of the dissipation also depends on the frequency or the probability of occurrence of the transitions. If a high probability of transitions is assumed and correspondingly low supply and threshold voltages chosen, to reduce the transitions component of the power dissipation and provide acceptable noise margins. respectively, the increase in the static dissipation may be large. As the supply voltage is reduced, the power-delay product of CMOS circuits decreases and the delays increase monotonically. Hence, while it is desirable to use the lowest possible supply voltage, in practice, only as low a supply voltage can be used as corresponds to a delay that can be compensated by other means, and steps can be taken to retain the system level throughput at the desired level. One way of influencing the delay of a CMOS circuit is to change the channel-width to channel-length ratio of the devices in the circuit. The power-delay product for an inverter driving another inverter through an interconnect of certain length varies with the width to length ratio of the devices. If the interconnect capacitance is insignificant, the power-delay product initially decreases and then increases when the width-to-length ratio is increased and the supply voltage is reduced to keep the delay constant. Hence, there exists a the supply voltage and the width-to-length ratio that is optimal from the power-delay product consideration. The way to assure that the system level throughput does not degrade as supply voltage is reduced by exploiting parallelism a