The HDL example design provides bas

The HDL example design provides basic loopback functionality on the user side of the AXI Ethernet Subsystem and connects the GMII/RGMII interface to external IOBs. The design also operates as a pattern generator with optional PHY-side external data loopback with automaticchecking.This configuration allows the functionality of the subsystem to be demonstrated either by using a simulation package as discussed in this guide, or directly in hardware when placed on a suitable board. The simple state machine assumes standard AMD demonstration board PHY address and register content