The clamper circuit that we used al

The clamper circuit that we used also seemed to have some issues as well.In hindsight, it is possible that this circuit element should have been eliminated.Its purpose was to increase the area to be integrated later on by clamping the bottom of the signal to ground.Unfortunately, we also observed that since the noise was clamped to ground as well, instead of the noise being centered on ground and canceling itself out in the integration it added a significant positive contribution.The result of this integration was a constant, which does not effect the quality of the result(DC is filtered), but it does reduce the dynamic range that remains for the output of the integrator to work with.If the clamper was eliminated, then the multiplier circuit would likely need to be redesigned to support input voltages that were both positive and negative.The simplest solution may be to use an analog multiplexer IC rather than designing one, although this could be done using more MOSFETs.The integrator seemed to work properly other than the non-ideality we observed with the reset operation.It appeared that the integrator may not have been reset to exactly 5V every time.Further investigation into this area would be necessary.One possible cause of this problem is insufficient time allotted to discharge the capacitor.Another issue that we had in this stage of the circuit was the fact that since the dsPIC’s ADC drew more current than expected we needed to add a transistor for current gain.We never determined why the dsPIC drew so much current, as ideally an ADC input would have high impedance.Making the dsPIC code more dynamic would be a big improvement.Global variables at the start of the program to allow easy adjustment of the sampling frequency and the PWM frequency would be an advantage.