Associated with each operation is a

Associated with each operation is a latency. When inputs FSELECT/PSEL change value, there is a pipeline delay before control is transferred to the selected register; there is a pipeline delay before the analog output is controlled by the selected register. When times t11 and t11A are met, PSEL0, PSEL1, and FSELECT have latencies of six MCLK cycles when SYNC = 0. When SYNC = 1, the latency is increased to 8 MCLK cycles. When times t11 and t11A are not met, the latency can increase by one MCLK cycle. Similarly, there is a latency associated with each write operation. If a selected frequency/phase register is loaded with a new word, there is a delay of 6 to 7 MCLK cycles before the analog output will change (there is an uncertainty of one MCLK cycle regarding the MCLK rising edge at which the data is loaded into the destination register). When SYNC = 1, the latency is 8 or 9 MCLK cycles.