Loopback functionality is provided as either MAC RX to TX (loopback logic replaces the packet generator as the packet source), or PHY TX to RX (loopback logic replaces the demonstration test bench stimulus and checker). Push buttons and DIP switches on the board provide basic control of the state machine allowing Ethernet MAC bit rate change. See the board-specific sections in Targeting the Example Design to a Board. The following figure illustrates the top-level of the AXI Ethernet Subsystem HDL example design.