It can be seen that the PLL clock i

It can be seen that the PLL clock is derived from a crystal oscillator or an external clock source and external loop filters (pllf1 and pllf2) to suppress signal jitter and interference. The DSP chip operating clock source forms an external clock signal generated by the frequency phase locked loop. There are two different clock domains, LF2407A:
(1) CPU clock. It is the internal logic of the CPU that uses the most clocks. It is formed by doubling the phase-locked loop doubling of the external clock signal of the frequency, and is reset by the system control register SCSR1 and the default value is 0.5 times.
(2) System clock. It is mainly a peripheral clock and CPU clock interrupt. Among them, the peripheral clock is mainly to establish internal and external chips (such as ADC, SCI, etc.) services, which can be separately set and output by the CPU clock output clock. The CPU is used to interrupt the clock interrupt service.
The clock WDCLK in the watchdog (watchdog) circuit is from the CLKOUT clock.
4) Reset circuit
The LF2407A has two reset sources, an external reset pin reset and a watchdog reset. The external reset pin RS (133) is an I/O pin. The normal state is connected to the power supply through a pull-up resistor. When an internal reset event occurs, the pin is driven low and the other chips in the system provide a reset signal. When an external reset event (manual reset, reset, reset, undervoltage, etc.), the pin is in input mode while The reset interrupt vector 0000h is loaded into the PC program counter and the program execution is restarted.
The watchdog is actually a timer circuit. The timer is characterized by an automatic counting circuit as long as it is enabled. It must be reset again within the specified time, counting from zero, or the full timer overflow will generate a system reset interrupt. Therefore, under normal circumstances, the program should continue to reset the watchdog timer in different places within the specified time, and the timer will not overflow due to the reset signal. When the program runs or crashes, the watchdog timer is reset to reset, the system will overflow, and the system will resume from a chaotic state to a reset state. Therefore, the watchdog circuit improves the reliability and integrity of the system.
The LF2407A features a power-on reset, brown-out reset, and manual reset. The system uses it to implement the external reset signal management function. The reset signal output pin is connected to the RS reset pin DSP. The circuit is shown in Figure 2-4. In the operation of the system, even if a collision occurs, there may be interference and interference. At this point, it is very convenient to use hardware to solve the problem.