All registers are 32-bit wide, acce

All registers are 32-bit wide, accessible via OCP interface with 16-bit or 32-bit OCP access (Read/Write).The 32-bit registers write update in 16 bits access must be LSB16 first and the second write access mustbe MSB16. For the write operation, the module allows skipping the MSB access if the user does not needto update the 16 MSB bits of the register, but only for the OCP registers (TIDR, TIOCP_CFG,IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR, IRQWAKEEN and TSICR). Thewrite operation on any functional register (TCLR, TCRR, TLDR, TTGR and TMAR) must be complete (theMSB must be written even if the MSB data is not used).