Table 6-1 is a truth table that pro

Table 6-1 is a truth table that provides the logic level definitions of operation modes.In the case where HINx and LINx pin signals in each phase are high at the same time, both the high- and low-sidetransistors become on (simultaneous on-state). Therefore, HINx and LINx signals, the input signals for the HINx andLINx pins, require dead time setting so that such a simultaneous on-state event can be avoided.After the IC recovers from a UVLO_VCC condition, the low-side transistors resume switching in accordance with theinput logic levels of the LINx signals (level-triggered), whereas the high-side transistors resume switching at the nextrising edge of an HINx signal (edge-triggered).After the IC recovers from a UVLO_VB condition, the high-side transistors resume switching at the next rising edgeof an HINx signal (edge-triggered).