The timer can be configured to prov

The timer can be configured to provide a programmable pulse-width modulation (PORTIMERPWM)output. The PORTIMERPWM output pin can be configured to toggle on a specified event. TCLR (TRGbits) determines on which register value the PORTIMERPWM pin toggles. Either overflow or match can beused to toggle the PORTIMERPWM pin, when a compare condition occurs.In case of overflow and match mode, the match event will be ignored from the moment the mode was setup until the first overflow event occurs (see Capture Wave Example for CAPT_MODE = 1).The TCLR (SCPWM bit) can be programmed to set or clear the PORTIMERPWM output signal while thecounter is stopped or the triggering is off only. This allows fixing a deterministic state of the output pinwhen modulation is stopped. The modulation is synchronously stopped when the TRG bit is cleared andan overflow has occurred.In the following timing diagram, the internal overflow pulse is set each time (FFFF FFFFFh – TLDR + 1)value is reached, and the internal match pulse is set when the counter reaches TMAR register value.According to TCLR (TRG and PT bits) programming value, the timer provides pulse or PWM on the outputpin (PORTIMERPWM).The TLDR and TMAR registers must keep values smaller than the overflow value (FFFF FFFFh) with atleast 2 units. In case the PWM trigger events are both overflow and match, the difference between thevalues kept in TMAR register and the value in TLDR must be at least 2 units. When match event is used,the compare mode TCLR (CE) must be set.