For shared logic connectivity guide

For shared logic connectivity guidelines, see Table 3-1 in the 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).For Clock Management with Multiple Core Instances for SGMII, see the “Clock Sharing Across Multiple Cores with Transceivers and FPGA Logic Elastic Buffer” section in 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).