The phase and frequency registers to be used are selected using the FSELECT, PSEL0, and PSEL1 pins, or the corresponding bits can be used. Bit SELSRC determines whether the bits or the pins are used. When SELSRC = 0, the pins are used, and when SELSRC = 1, the bits are used. When CLR is taken high, SELSRC is set to 0 so that the pins are the default source. Data transfers from the serial (defer) register to the 16-bit data register, and the FSELECT and PSEL registers, occur following the 16th falling SCLK edge.