Interrupt ControllerThe Nested Vect

Interrupt ControllerThe Nested Vectored Interrupt Controller (NVIC) is an integral part of Cortex-M0,which is tightly coupling to the MCU. The NVIC supports 32 vectored interruptand 4 programmable interrupt priority levels. External interrupts need to be enabled before being used. If an interrupt is not enabled, or if the processor is already running another exception handler with same or higher priority, the interrupt request will be stored in a pending status register. The pended interrupt request can be triggered when the priority level allowed for example, when a higher-priority interrupt handler has been completed and returned. The NVIC can accept interrupt request signals in the form of logic level, as well as an interrupt pulse (with a minimum of one clock cycle). The NVIC supports stacking and unstacking processor status automatically. Do not need ISR to handles this. The NVIC supports vectored interrupt entry. When an interrupt occurs, the NVIC automatically locates the entry point of the interrupt service routine from a vector table in the memory. For detailed information about NVIC, please refer to “ARM® Cortex™-M0 Technical Reference Manual” and “ARM® v6-M Architecture Reference Manual”.