Figure 12-3 is a timing diagram des

Figure 12-3 is a timing diagram describing how noiseor other detrimental effects will improperly influence thelevel-shifting process. When a noise-induced rapidvoltage drop between the VBx and output pins (U, V, orW1; hereafter “VBx–HSx”) occurs after the Set signalgeneration, the next Reset signal cannot be sent to the SRflip-flop circuit. And the state of an HOx signal stayslogic high (or “H”) because the SR flip-flop does notrespond. With the HOx state being held high (i.e., thehigh-side transistor is in an on-state), the next LINx signalturns on the low-side transistor and causes asimultaneously-on condition, which may result in criticaldamage to the IC. To protect the VBx pin against such anoise effect, add a bootstrap capacitor, CBOOTx, in eachphase. CBOOTx must be placed near the IC and beconnected between the VBx and HSx pins with a minimallength of traces. To use an electrolytic capacitor, add a0.01 μF to 0.1 μF bypass capacitor, CPx, in parallel nearthese pins used for the same phase.