在高速信号传输过程中，传输速率的加快会导致数据的误码率以及时钟抖动不断

In the high-speed signal transmission process, the transmission rate will result in accelerated data clock jitter and the error rate increasing, the receiving side even cause data errors. To reduce the clock jitter adversely affect the recovery data receiving end, to provide a 10Gb / s low jitter clock data recovery circuit. By addition of a pseudo-random data encoding (PRBS31) simulation test, the receiver bit error rate is less than 10-12, the total power consumption is 94mW, corresponding to the recovered data clock jitter peak value 2.94ps. Compared to a conventional clock data recovery circuit which jitter desired effect is achieved by increasing the debounced input data and to reduce the clock phase detector. It may be used in the data receiving end to recover the higher data transmission rates (8.3Gb / s-10Gb / s) data clock.

In the process of high-speed signal transmission, the acceleration of transmission rate will lead to the error rate of data and clock jitter increasing, and even cause the receiving data error. In order to reduce the adverse effect of clock jitter on the recovery of receiving data, a 10Gb/s ultra-low jitter clock data recovery circuit is proposed. By adding pseudo-random data encoding (PRBS31) for simulation testing, the receiving error rate is less than 10-12, the total power consumption is 94mW, and the recovery of data corresponds to a peak of 2.94ps. Compared to the traditional clock data recovery circuit, the circuit achieves the desired effect by increasing the digestion of input data and reducing the clock jitter of the phase-picker. Data clocks with high data transfer rates (8.3Gb/s-10Gb/s) can be recovered at the data receiver.

In the process of high-speed signal transmission, the acceleration of transmission rate will lead to the increase of data error rate and clock jitter, and even the data error at the receiving end. In order to reduce the adverse effect of clock jitter on receiver data recovery, a 10Gb / s ultra-low jitter clock data recovery circuit is proposed. By adding pseudo-random data coding (prbs31) to the simulation test, the bit error rate of the receiver is less than 10-12, the total power consumption is 94mw, and the peak value of clock jitter corresponding to the recovered data is 2.94ps. Compared with the traditional clock data recovery circuit, the circuit achieves the desired effect by increasing the input data jitter and reducing the clock jitter of the phase detector. It can be used in the data receiver to recover the data clock with high data transmission rate (8.3gb/s-10gb / s).<br>