Transfers initiated by a read of the Rx FIFO depend on the number of bytes received in the FIFO. If IRQMODE is set to 7 and a read to the Rx FIFO occurs, the SPI initiates an 8-byte transfer. If continuous mode is set, the eight bytes occur continuously with no de-assertion of CS0/1/2 between bytes. If continuous mode is not set, the eight bytes occur with stall periods between transfers where CS0/1/2 is deasserted (pulled high). However, in continuous mode, if CNT[13:0] is greater than 0, then CS0/1/2 will be asserted for the entire frame duration. SPI will introduce stall periods by not clocking SCL until FIFO space is available