If A / D conversion is to be performed, the CS enabling terminal needs to be placed at a low level and kept at a low level until the conversion is complete. At this point, the chip begins the conversion, and the processor inputs the clock pulses to the chip clock input Terminal Clk, and the DO / Di Terminal uses the data signal selected by the DI input channel function. The DI terminal must be at a high level before the first clock pulse sinks, indicating the start signal. Before the second or Third Pulse Sinks, the Di Terminal should input 2 bits of data to select the channel function.