Figure 30 shows the serial interface between the AD9832 and the 80C51/80L51 microcontroller. The microcontroller operates in Mode 0 so that TXD of the 80C51/80L51 drives SCLK of the AD9832, while RXD drives the serial data line SDATA. The FSYNC signal is again derived from a bit programmable pin on the port (P3.3 being used in the diagram). When data is transmitted to the AD9832, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes; therefore, only 8 falling SCLK edges occur in each cycle. To load the remaining 8 bits to the AD9832, P3.3 is held low after the first 8 bits have been transmitted and a second