Transfer of the data from the 16-bi

Transfer of the data from the 16-bit data register to the destination register or from the FSELECT/PSEL register to the respective multiplexer occurs on the next MCLK rising edge. Because SCLK and MCLK are asynchronous, an MCLK rising edge may occur while the data bits are in a transitional state. This can cause a brief spurious DAC output if the register being written to is generating the DAC output. To avoid such spurious outputs, the AD9832 contains synchronizing circuitry. When the SYNC bit is set to 1, the synchronizer is enabled and data transfers from the serial register (defer register) to the 16-bit data register, and the FSELECT/PSEL registers occur following a two-stage pipeline delay that is triggered on the MCLK falling edge. The pipeline delay ensures that the data is valid when the transfer occurs. Similarly, selection of the frequency/phase registers using the FSELECT/PSELx pins is synchronized with the MCLK rising edge when SYNC = 1. When SYNC = 0, the synchronizer is bypassed. Selecting the frequency/phase registers using the pins is synchronized with MCLK internally also when SYNC = 1 to ensure that these inputs are valid at the MCLK rising edge. If times t11 and t11A are met, then the inputs will be at steady state at the MCLK rising edge. However, if times t11 and t11A are violated, the internal synchronizing circuitry will delay the instant at which the pins are sampled, ensuring that the inputs are valid at the sampling instant (see Figure 5).