In general, there are four data lin

In general, there are four data lines between ADC0832 and STC89C52, which are CS data line, CLK data line, do data line and di data line. Because do end and di end can't take effect at the same time, and the interface of STC89C52 is bidirectional. So in the circuit design, we can connect do data line and di data line in parallel, so that they are on one data line. When ADC0832 is not working, the input of its CS data line is high level. At this time, the chip will be forbidden to use, and the level of CLK data line and do / di data line can be arbitrarily changed. If we want to carry out a / D conversion, we must first put the CS data line terminal at the low level, and we must also keep the low level until the A / D conversion is completed. When the chip starts a / D conversion, the processor should input clock pulse to CLK, and the do / di data line end needs to use the di data line end to input the data signal selected in the channel function. The prompt of the starting signal is that before the sinking of the first clock pulse, the di data line terminal must be high level. The function of selecting channel shall input 2 bits of data at di end before the second and third pulse sinks.