During the design of Ncore, several tools were used tomodel and verify Ncore’s performance. An instruction simulatorwas developed as the golden model to drive hardwareverification efforts and verify correctness of assemblygenerated by the libraries. Prototyping algorithms with newSIMD instructions, changes to the machine width, and changesto RAM sizes were modeled using a custom C++ vectorclass library (VCL). The VCL provided a path for quick