Out circuit was designed assuming t

Out circuit was designed assuming the clamper output would stay above ground.As predicted, the integrator integrates downward until it is reset to 5V by the PMOS.Although the output of the multiplier was not ideal, it still had an amplitude linearly proportional to the audio signal, so the integration should still work in theory.When the reset switch opens, returning the integrator to normal mode, there is a voltage spike observed.This should not affect the dsPIC’s reading however, since it only samples right before the reset switch is activated.There is a potential issue in that the integrator seems to jump to some voltage that is not 5V right before it starts integrating.This may be due to the capacitor not fully charging to 5V.This was an issue that time did not permit us to fully investigate.In this section we will illustrate how the dsPIC performed its functions when the circuit was actually implemented.We will examine the functionality of the dsPIC step by step and explain any differences between actual and ideal behavior.First we will look at how the performance of the clocks and the reset switch.Then we will look in depth on how the pulse width modulation performed.The clock signals are shown below in the figure below.It can be seen that they are out of phase with each other to allow for proper multiplication and modulation functionality in the rest of the circuit.The final modulation frequency that we achieved was 100Khz.Normally when the ADC interrupt is called the clock continues to be modulated with a slower square wave during the delay times.In figure:shown below we have taken out the modulation so that we could trigger the wave form and shown the length of the interrupt is roughly ¼ of the total period.This is because the interrupt doubles as a PWM pulse.The sampling frequency of out system can also be derived from figure:below.The time between when the ADC interrupt is called is the period and it is roughly 550 micros seconds, which translates into a 2000Hz sampling frequency.Our implementation was meant to have a 4000KHz sampling rate to account for the human hearing range.We turned down the frequency for our final demonstration because we were only trying to detect 60Hz which does not need such a high sampling rate.Also the amount of square wave integrations doubled so we could get a more accurate signal.The sampling frequency can be turned back up to 4000KHz by sampling changing a configuration bit.The waveform for the reset signal is shown in the figure below.The reset signal was high to keep the MOSFET as an open circuit while the capacitor in the integrator charged.When the ADC interrupt is called the integral has been sampled and converted to a quantized number.If you look at periods of the signals in figure:above and figure:below you can see that the reset of the integral takes place during the ADC interrupt.While the ADC interrupt is computing the new PWM duty cycles the capacitor is discharging.When the ADC interrupt finishes the reset signal is set high again and the capacitor charges.The pulse width modulation module performed well.Figure:shown below is an input test signal at 300Hz from a function generator and the resulting output waveform of the PWM.The PWM behaves as it should; the pulses get longer when the input sinusoid is higher in amplitude.The only discrepancy between the observed PWM output and ideal is that the PWM wave form is delayed.The reason for this delay lies in the nature of the PWM code.The value read into the ADC is not actually implemented until one cycle after it is read.A small delay in listening to an audio signal would not be perceptible to a user, and is therefore perfectly acceptable.Another behavior to note is that because we had to half the sampling frequency to 2000Hz down from 4000Hz the frequency of the PWM when from 16 KHz down to 8 KHz.The reconstruction filter is designed to filter out the high frequency PWM pulses and leave the low frequency information that is related to the width of the pulses.Ideally the PWM frequency would be out of the range of human hearing but because we had to lower the clock frequency the PWM frequency became very audible to the human ear.Figure:illustrates the PWM waveform from the 300Hz test signal and the resulting waveform after the low pass filter.The PWM pulses line up better with this waveform then with the input because there is less of a delay.There still is some delay that is associated with phase delays in the low pass filter.The output waveform is also very choppy.This behavior is due the fact that the PWM frequency is so low that some of it still ends of in the output of the low pass filter.If you were to zoom in you could see faint remnants of the 8000Hz PWM pulses.The figure shown above is the input waveform from the function generator above, and the output waveform of the PWM passed through the low pass filter.