The AD9832 has a serial interface, with 16 bits being loaded during each write cycle. SCLK, SDATA, and FSYNC are used to load the word into the AD9832. When FSYNC is taken low, the AD9832 is informed that a word is being written to the device. The first bit is read into the device on the next SCLK falling edge with the remaining bits being read into the device on the subsequent SCLK falling edges. FSYNC frames the 16 bits; therefore, when 16 SCLK falling edges have occurred, FSYNC should be taken high again. The SCLK can be continuous, or alternatively, the SCLK can idle high or low between write operations.