The axis_clk signal should be conne

The axis_clk signal should be connected to the same clock source as the AXI4-Stream interface. When using a FIFO, axis_clk should be connected to the AXI_lite clock of the FIFO; for the DMA this needs to be connected to the same clock source as m_axi_mm2s_aclk and m_axi_s2mm_aclk of DMA.The Run Connection Automation command connects the AXI4-Lite interface of the subsystem to the peripheral interface of the processor. This also connects the AXI4-Lite clock and the AXI4-Lite reset to the respective sources. When the project is set for a board that has the related interfaces, the Run Connection Automation command also connects the I/Os to external I/O ports by creating them and providing the LOC constraints.